Design of multi-precision reconfigurable Wallace Tree Multiplier for high performance applications
نویسنده
چکیده
We designed reconfigurable 8x8 multiplier architecture in 180nm with 1.8 power supply based on Wallace Tree, efficient in power and regularity without increase in delay and area. The idea is the generation of partial products in parallel using AND gates. The addition of partial products is reducing using Wallace Tree which is hierarchically divided into levels. Therefore there will be a significant reduction in the power consumption, since power is provided only to the level that is involved in computation and the remaining two levels switched off. To improve the speed of addition at the final level of computation, a carry look-ahead adder (CLA) is used which is better in terms of area/speed.
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تاریخ انتشار 2012